1. Field of the Invention
The present invention relates to improvement of a conductive layer for a power voltage V.sub.DD or a ground voltage V.sub.SS using a multilayer plastic package and a multilayer ceramic package such as a pin grid array package (PGA).
2. Description of the Related Art
Conventionally, in a multilayer ceramic package such as a pin grid array package (PGA), a conductive layer (hereinafter called simply as conductive layer) for supplying a power voltage V.sub.DD or a ground voltage V.sub.SS to a semiconductor device (IC chip) is structured as shown in FIG. 1.
That is, in FIG. 1, a conductive layer 11 comprises a square layer-like conductor. In the central portion of the conductive layer 11, a square hole is formed. In the end portion of the inside of the conductive layer 11, contact points 12 to be connected to an inner lead are formed. The contact points 12 are irregularly arranged due to a bonding pad formed in the inner lead. Therefore, the distance among the contact points 12 differs.
In the end portion of the outside of the conductive layer 11, contact points 13 to be connected to an outer lead for a power voltage source or a ground pin are formed. The contact points 13 are irregularly arranged due to the other outer lead for a signal pin. Therefore, similar to the contact points 12, the distance among the contact points 13 differs.
In the conventional multilayer ceramic package, the positions and the number of the contact points 12 and 13 are determined regardless of the shape of the conductive layer 11. In other words, in conventional, neither the rule of the arranging method of the contact points 12 and 13 nor the rule of the setting method of the number of the leads exists.
In the state that no constant rule exists, if a plurality of output buffers, which are formed in the IC chip in the package, are turned on at the same time, a large current must be supplied to the IC chip during a short period of time in order to normally drive the plurality of the output buffers. In this case, in the conventional package, the current flowing in the conductive layer 11 becomes uneven, the power voltage V.sub.DD or the ground voltage V.sub.SS largely varies. This variation becomes the so-called simultaneous switching noise, thereby causing an erroneous operation of an input buffer or that of a logic circuit.
FIG. 2 shows a distribution of current density of the conductive layer 11 for the ground voltage V.sub.SS and current is dense in an area D.